Hi, I'm Redwan, a Principal VLSI Engineer from Dhaka, Bangladesh.

Logical and Physical Synthesis 

• Experience with Logical & Physical Synthesis using Cadence Genus, Synopsys Design Compiler (DC and DC Topography) and Fusion Compiler (FC).

• Experience with writing and debugging hierarchical leaf block level and chip/mega-block level timing constraints (SDC).

• RTL Feedback

PD implementation and signoff tape-out experience

• PNR in TSMC (N5, N6, N7), Samsung (4lpp, 8lpp, 14nm), 28nm, 45nm technologies 

• Experience with PD implementation and signoff tape-out experience with Synopsys IC Compiler II, Cadence Innovus, ATopTech/Avatar Aprisa, Synopsys/Magma Talus.

• Place and Route experience with more than 35 complex blocks implementation, including blocks with analog IPs for tape-out.

Experience with multi-voltage designs (multi power domain PD blocks) driven by UPF/CPF and under IEEE 1801 Standard.

• Writing and validating power intent file (UPF).

• PNR Implementation of voltage islands with Level Shifter and other PNR methodology/flow development and implementation.

• Design closure to meet the power intention using Conformal and VC-LP Static check.

Expertise on physical integration of analog and digital IP

• Experience with integrating and implementing in-chip monitoring and sensing modules such as Process Detector (PD), Voltage Monitor (VM), Thermal/Temperature Sensor (TS), Critical Dimension Monitoring Macro (CDMM), Dummy TCD (DTCD) at block level. 

• Physical integration of high-speed DDR PHY 4 and 5, PCIe PHY, Ethernet PHY and Multi-Protocol SerDes with control logic at block level and C4 Bump assignment and RDL routing at the top level.

• Experience in implementation of EFUSE IP and related ESD Protection and custom power network.

• ESD Protection for ASIC/SoC Core and Special Purpose IPs.

• Experience with block level signoff for tapeout using STA, PV, IREM, LEC etc. tools by Cadence, Synopsys, Mentor, Ansys.

• Experience with block level and full chip level MMMC Static Timing Analysis using PrimeTime (PTSI), Tempus following extraction using StarRC, QRC. Worked on running, analyzing, and writing timing ECOs manually and from DMSA Timing ECO for fixing blocks and chip level timing requirement.

• Experience with running, analyzing, and fixing Physical Verification (PV) DRC, LVS, ANT, XOR for signoff using Mentor Calibre, Synopsys ICV, Cadence PVS. 

• Experience with running Cadence Voltus and Ansys/Apache Redhawk tools for Static and Dynamic IR, Power, and Signal Electromigration (EM) and analyze violations for fixing layout for tapeout.

• Experience with functional and power intent verification using Formality (FM), Verification Compiler Low-power Static (VCLP/ST).

Experience with multiple SoC level PNR design planning, exploration, implementation,

• Floorplan, Partition, Pin assignment, Block shaping, 

• Power routing, 

• Custom clock tree implementation, 

• High speed data bus implementation,

• General Purpose IO and other IP placement

• Bump placement, RDL routing etc.

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Experience in RTL2GDSII Physical Design (PD/PNR) Implementation Flow development and enhancement

• For Synopsys tools (Fusion Compiler, IC Compiler II, Design Compiler) using GNU Make/Makefile based automation

• For Cadence tools (Innovus, Encounter, Genus) using Stylus Flowtool/Flowkit 

• With Git-SCM based version control.

Experience in development and sole ownership of Synopsys Fusion Compiler chip top level and hierarchical design planning flow for TSMC N5 technology with Synopsys library and several leading Analog IP Vendors’ libraries.

Experience in development and sole ownership of Cadence Innovus design planning and exploration flow for chip top level and hierarchical designs using Samsung ln04lpp technology with traditional GNU make based approach and flowkit/flowtool approach.

Experience with writing and validating power delivery network scripts with multiple power domains and IP requirements on layout.